1. Field of the Invention
The present invention relates to a scan register and a testing circuit using the same, and particularly to a scan register and a testing circuit using the same for facilitating tests of semiconductor integrated circuit devices.
2. Description of the Background Art
For example, as shown in IEEE 1987 INTERNATIONAL TEST CONFERENCE CH2347-2 p.p. 105-110 "TESTING OF EMBEDDED RAM USING EXHAUSTIVE RANDOM SEQUENCES" by H. Maeno et al., and IEEE 1978 SEMICONDUCTOR TEST CONFERENCE 78CH 1409-2C p.p. 98-102 "DESIGNING DIGITAL CIRCUITS WITH EASILY TESTABLE CONSIDERATION" by S. Funatu et al., conventionally, a plurality of scan registers are connected to configure a scan path, and semiconductor integrated circuit devices are tested by this scan path. FIG. 1 is a block diagram showing a configuration of a test system using a scan path which the present applicant previously proposed in U.S. application Ser. No. 07/207,919. In the figure, a scan path 1 is provided between a first semiconductor device (a RAM in the figure) 2 and a second semiconductor device (a logic circuit in the figure) 3 on a semiconductor chip SC. This scan path 1, as shown in FIG. 2, comprises a plurality of scan registers SR1 through SRn. Each of the scan registers SR1 through SRn receives parallel output data from the RAM2 as input data P1. Output data PO from each of the scan registers SR1 through SRn are supplied to the logic circuit 3. Scan registers SR1 through SRn are connected in series, and configured to supply output data SO from a scan register at an adjacent previous stage as input data SI to the next one.
Next, the operation of the scan path 1 shown in FIGS. 1 and 2 will be described briefly.
First, in a normal mode, each of the scan registers SR1 through SRn is in a through state, and supplies parallel output data provided from the RAM 2 to the logic circuit 3 as it is received. In other words, each of the scan registers SR1 through SRn supplies the received input data PI as output data PO to the logic circuit 3. Thus, the logic circuit 3 operates in response to the data read from the RAM 3.
Next, in a first test mode testing the RAM 2, a test is performed by writing test data of logic "1" or "0" in all addresses of the RAM 2 and then reading them out. Thus, logic "1" or "0" is written into each of the addresses of the RAM 2 in advance. In this condition, in the scan register SR1 at the first stage of the scan path 1, expected value data are inputted serially from a LSI tester LT. These expected value data are of the same logic as those of test data written into the RAM 2. Scan registers shift each time a bit of expected value data is provided, and finally, expected value data are set in all of the scan registers SR1 through SRn. Each of the scan registers SR1 through SRn compares the set expected value data with the parallel output data read from the RAM 2 and determines whether they coincide with each other or not. As a result of the determination, when an error occurs in a certain bit of the parallel output data from the RAM 2, the logic of the expected data set in the scan register corresponding to the bit is inverted. After that, data set in respective scan registers SR1 through SRn are sequentially shifted by serial shift operations and provided as test results from the scan register SRn at the final stage to a LSI tester LT. By analyzing the test results by a test result determination circuit (not shown) provided in the LSI tester LT, it can be readily determined whether the RAM 2 is normal or not.
Next, in a second test mode testing the logic circuit 3, test data is serially supplied into the scan register SR1 at the first stage of the scan path 1 from the LSI tester LT. As in the case of the expected data, each of the scan registers shifts each time a bit of data is provided, and finally, test data are set in all of the scan registers. The test data set in respective scan registers SR1 through SRn are supplied to the logic circuit 3 as output data PO. Thus, by checking operation by the LSI tester LT based on outputs of the logic circuit 3 for seeing if desired operations according to this test data are performed in the logic circuit 3, it can be known if the logic circuit 3 is normal or not.
FIG. 3 is a circuit diagram illustrating a configuration of a scan register shown in FIG. 2. In the figure, a first input terminal 4 is a terminal which receives the input data SI shown in FIG. 2, a first output terminal 5 is a terminal which outputs the output data SO shown in FIG. 2, a second input terminal 6 is a terminal which receives the input data PI shown in FIG. 2, and a second output terminal 7 is a terminal which provides the output data PO shown in FIG. 2. In the following description herein, the first input terminal 4 is referred to as a serial input terminal, the first output terminal 5 as a serial output terminal, the second input terminal 6 as a parallel input terminal, the second output terminal 7 as a parallel output terminal, respectively.
A shift register stage 8 is provided between the serial input terminal 4 and the serial output terminal 5. A MOS transistor (referred to simply as a transistor hereinafter) 83, a latch circuit 81, a transistor 84 and a latch circuit 82 are connected serially to configure this shift register. At the gates of the transistors 83 and 84, shift clock signals .phi.1 and .phi.2 are supplied, respectively. The latch circuit 81 is a ratio type latch circuit which is composed of two inverse-parallel connected inverter circuits 81a and 81b. Likewise, the latch 82 is also a ratio type latch circuit, which is composed of two inverse-parallel connected inverter circuits 82a and 82b. The inverter circuit 81a has greater current handling capability than the inverter circuit 81b. The inverter circuit 82a has greater current handling capability than the inverter circuit 82b. The output of the shift register stage 8 at the output of the inverter circuit 82a, is supplied to the parallel output terminal 7, as well as to the serial output terminal 5. The determination circuit 9 comprises an exclusive NOR gate 91 and a NOR gate 92. The output of the inverter circuit 82a is supplied to one input terminal of the exclusive NOR gate 91 and the input data PI is supplied from the parallel input terminal 6 to the other input terminal thereof. A negative clock signal CMP is supplied to one input terminal of the NOR gate 92, the output of the exclusive NOR gate 91 is supplied to the other input terminal thereof. The output of the NOR gate 92 is supplied to the gate of the transistor 10. This transistor 10 is provided between the parallel input terminal 6 and the input terminal of the inverter circuit 81a. A transistor 11 is also connected in parallel with the transistor 10 between the parallel input terminal 6 and the input terminal of the inverter circuit 81a.
Next, the operation of the scan register shown in FIG. 3 will be described.
First, in the normal mode, the transistor 11 and 84 are always in an ON state. Therefore, the input data PI from the parallel input terminal 6 is provided from the parallel output terminal 7 through the transistor 11, the latch circuit 81, the transistor 84 and the latch circuit 82. At this time, the input data PI from the parallel input terminal 6, after its logic is inverted by the inverter circuit 81a, is inverted again by the inverter circuit 82a, so that the output data PO of the parallel output terminal 7 is of the same logic as that of the input data PI from the parallel input terminal 6.
Next, in the first test mode testing the RAM 2 (shown in FIG. 1), expected value data is supplied first at the serial input terminal 4. At this time, at the gates of the transistors 83 and 84, two-phase shift clock signals .phi.1 and .phi.2, respectively, are supplied, which does not overlap with each other. Accordingly, the shift register stage 8 shifts the provided expected value data. As the shift operations are completed, data of the same logic as that of the provided expected value data is set at the output terminal of the latch circuit 82, or the output terminal of the inverter circuit 82a. Next, data is read from the RAM2 and supplied to the parallel input terminal 6. The exclusive NOR gate 91 compares the output data of the inverter circuit 82a with the input data PI from the parallel input terminal 6 and, when the logics of both data coincide with each other, the logic of its output is "1". Thus, even if the negative clock signal CMP supplied at one input terminal of the NOR gate 92 becomes active ("L" level), its output remains at "L" level (logic "0"). Accordingly, the transistor 10 remains in an OFF state and the input data PI from the parallel input terminal 6 is not supplied to the shift register stage 8. On the other hand, when the logics of the output data of the inverter circuit 82a and the input data PI from the parallel input terminal 6 do not coincide with each other, the output of the exclusive NOR gate 91 becomes "0". Therefore, when the negative clock signal CMP supplied to the NOR gate 92 becomes active ("L" level), its output becomes "H" level (logic "1"). As a result, the transistor 10 turns on and the input data PI from the parallel input terminal 6 is supplied to the latch circuit 81. Thus the input data PI from the parallel input terminal 6 is allowed into the latch circuit 81. Accordingly, at the input terminal of the inverter circuit 81a, data of the logic opposite to that of the expected value data is set. In other words, when the negative clock signal CMP is active, if data different from expected value data is supplied to the parallel input terminal 6 even once, data held in the latch circuit 81 composed of the inverter circuit 81a and 81b is inverted. Subsequently, the shift register stage 8 shifts. By this operation, the data held in the shift registers 8 of respective scan registers are obtained sequentially from the shift register SRn at the final stage.
Next, the operation in the second test mode testing the logic circuit 3 (refer to FIG. 1) will be described. First, test data is provided at the serial input terminal 4. At this time, the shift register stage 8 performs shift operations, and shifts the inputted data sequentially. When the shift operations are completed, test data are set in the latch circuit 81 and 82. Then, the output data of the inverter circuit 82a is of the same logic as that of the test data. The output data of this inverter circuit 82a is supplied to the logic circuit 3 through the parallel output terminal 7.
As described above, by employing scan registers, without requiring reading data from the RAM 2 by serial shift operations for each address, the RAM 2 can be tested efficiently. Also, by serial shift operations of the scan path 1, any data can be supplied to the parallel output terminal 7, so the logic circuit 3 connected on the output side of the RAM 2 can be readily tested.
The scan register shown in FIG. 3, however, has two inverter circuits 81a and 82a provided between the parallel input terminal 6 and the parallel output terminal 7. Consequently, the signal propagation delay time from the RAM 2 to the logic circuit 3 in the normal mode is so large that it has a problem of performance degradation of semiconductor integrated circuit devices.